yosys

Framework for Verilog RTL synthesis and formal verification

brewmacoslinux

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Framework for Verilog RTL synthesis

yosysyosys-abc

Convert Verilog file to BLIF netlist$ yosys -p 'read_verilog design.v; write_blif design.blif'

Synthesize Verilog to target technology$ yosys -p 'read_verilog design.v; synth_ice40 -json design.json'

Run formal verification on Verilog design$ yosys -p 'read_verilog design.v; write_smt2 design.smt2'