verilator

Open-source Verilog simulator for hardware verification and testing

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Verilog simulator

verilator

Compile a Verilog module to C++ for simulation$ verilator --cc module.v --exe sim_main.cpp

Generate SystemVerilog coverage reports$ verilator --cc --coverage module.v --exe test.cpp

Simulate with waveform output in VCD format$ verilator --cc --trace module.v --exe sim.cpp && obj_dir/Vmodule