uhdm

Universal Hardware Data Model for SystemVerilog object model parsing

brewmacoslinux

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Universal Hardware Data Model, modeling of the SystemVerilog Object Model

uhdm

Parse a SystemVerilog file and generate UHDM model$ uhdm -parse input.sv

Dump the UHDM design hierarchy from a compiled model$ uhdm -dump design.uhdm

Compile SystemVerilog sources with UHDM integration$ uhdm -compile -o design.uhdm source1.sv source2.sv