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surelog

SystemVerilog parser and UHDM compiler for hardware design verification

brewmacoslinux
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About

SystemVerilog Pre-processor, parser, elaborator, UHDM compiler

Commands

sureloguhdm-dump

Examples

Parse and elaborate a SystemVerilog design file$ surelog -parse design.sv
Compile SystemVerilog to UHDM format$ surelog -compile -uhdm design.sv -top module_name
Dump UHDM database contents for inspection$ uhdm-dump output.uhdm