sby

Formal verification tool for hardware designs using Yosys

brewmacoslinux

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Front-end for Yosys-based formal verification flows

sby

verify hardware module against specification$ sby -f design.sby

check Verilog code for logical errors automatically$ sby design.sby

run formal verification with multiple solver engines$ sby --engine smtbmc design.sby

generate counterexample when verification fails$ sby -d output_dir design.sby

verify property holds for specific number of cycles$ sby --depth 100 design.sby