icarus-verilog

Compile and simulate Verilog hardware designs

brewmacoslinux

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Verilog simulation and synthesis tool

iverilogvvp

compile verilog code into executable simulation$ iverilog -o output.vvp design.v testbench.v

run verilog simulation and see output$ vvp output.vvp

check verilog syntax without running simulation$ iverilog -t null design.v

compile multiple verilog files together$ iverilog -o sim.vvp module1.v module2.v testbench.v

generate verilog netlist for synthesis$ iverilog -t rtlil -o netlist.il design.v